EFM32G-DK3550【PDF 363/467 页】KIT DEVELOPMENT EFM32 GECKO

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...the world's most energy friendly microcontrollers

25.5.13 ADCn_SCANDATAP - Scan Sequence Result Data Peek Register

Offset

0x030

Reset

Access

Name

Bit Position

Bit

31:0

Name

DATAP

Reset

0x00000000

Access

R

Description

Scan Conversion Result Data Peek

The register holds the results from the last scan conversion. Reading this field will not clear SCANDV in ADCn_STATUS or single

DMA request.

25.5.14 ADCn_CAL - Calibration Register

Offset

0x034

Reset

Access

Name

Bit Position

Bit

Name

Reset

Access

Description

31

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

30:24

SCANGAIN

0x3F

RW

Scan Mode Gain Calibration Value

This register contains the gain calibration value used with scan conversions. This field is set to the production gain calibration value

for the 1V25 internal reference during reset, hence the reset value might differ from device to device. The field is unsigned. Higher

values lead to higher ADC results.

23

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

22:16

SCANOFFSET

0x00

RW

Scan Mode Offset Calibration Value

This register contains the offset calibration value used with scan conversions. This field is set to the production offset calibration

value for the 1V25 internal reference during reset, hence the reset value might differ from device to device. The field is encoded as

a signed 2's complement number. Higher values lead to lower ADC results.

15

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

14:8

SINGLEGAIN

0x3F

RW

Single Mode Gain Calibration Value

This register contains the gain calibration value used with single conversions. This field is set to the production gain calibration value

for the 1V25 internal reference during reset, hence the reset value might differ from device to device. The field is unsigned. Higher

values lead to higher ADC results.

7

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

6:0

SINGLEOFFSET

0x00

RW

Single Mode Offset Calibration Value

2011-04-12 - d0001_Rev1.10

363

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